杭州著名外企招聘ASIC / FPGA 设计人员. 有兴趣者请发送简历至:
asic_cn@hotmail.com
ASIC designer
-Hand-on experience in ASIC front-end design and verification using Verilog or VHDL.
-Significant expertise in chip architecture, with fluency in Verilog / VHDL and script languages like Perl and Tcl.
-Background in telecom or security chip design are highly desirable.
-Hands-on experience with synthesis, static timing analysis, and design for test (DFT) tools.
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Senior FPGA designer
-3+ yrs hands-on experience with complete FPGA / ASIC design process including chip specification, Verilog / VHDL coding, synthesis, simulation, place and rout, FPGA test and integration;
-significant expertise in chip architecture;
-familiar with the latest FPGA device families and design tools;
-good working attitude and communication skills;
-background in ADSL/VDSL system, ATM SAR, layer 2 bridge and microprocessor based design, or background in security chip design are highly desirable.
asic_cn@hotmail.com
ASIC designer
-Hand-on experience in ASIC front-end design and verification using Verilog or VHDL.
-Significant expertise in chip architecture, with fluency in Verilog / VHDL and script languages like Perl and Tcl.
-Background in telecom or security chip design are highly desirable.
-Hands-on experience with synthesis, static timing analysis, and design for test (DFT) tools.
.-----------------
Senior FPGA designer
-3+ yrs hands-on experience with complete FPGA / ASIC design process including chip specification, Verilog / VHDL coding, synthesis, simulation, place and rout, FPGA test and integration;
-significant expertise in chip architecture;
-familiar with the latest FPGA device families and design tools;
-good working attitude and communication skills;
-background in ADSL/VDSL system, ATM SAR, layer 2 bridge and microprocessor based design, or background in security chip design are highly desirable.
