- 注册
- 2002-10-07
- 消息
- 402,174
- 荣誉分数
- 76
- 声望点数
- 0
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You will specify, architect, design and develop FPGA code for multi-gigabit/sec board-level products for packet classification, using patented technology, implementing classification solutions with Gigabit Ethernet, OC-48, OC-192 and beyond. You are able to identify and document the requirements for a large, complex FPGA, communicate the top-level design to your co-workers, and follow through with a rapid design and verification cycle that gets the board up and running. You are highly proficient in Verilog and/or VHDL, skilled with FPGA implementation and verification tools, especially Synplicity, Modelsim, Altera and Xilinx. You have mentored junior developers, and can solve the toughest problems in the lab. You are keenly aware of the importance of delivering quality products on time to customers. You have a proven track record of bringing successful projects to fruition; have proven leadership skills and excellent verbal and written communication ability.
Requirments:
BSEE and 5+ years full time Verilog/VHDL design experience, preferably in data communications
Complete FPGA designs using VHDL and/or Verilog HDL
Experience with Synplicity, Modelsim, large Xilinx and Altera devices
Proven track record of FPGA code from concept to production
SONET, POSPHY, Utopia, PCI bus, Gigabit Ethernet design experience is an asset
Contact: yilin@canada.com
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You will specify, architect, design and develop FPGA code for multi-gigabit/sec board-level products for packet classification, using patented technology, implementing classification solutions with Gigabit Ethernet, OC-48, OC-192 and beyond. You are able to identify and document the requirements for a large, complex FPGA, communicate the top-level design to your co-workers, and follow through with a rapid design and verification cycle that gets the board up and running. You are highly proficient in Verilog and/or VHDL, skilled with FPGA implementation and verification tools, especially Synplicity, Modelsim, Altera and Xilinx. You have mentored junior developers, and can solve the toughest problems in the lab. You are keenly aware of the importance of delivering quality products on time to customers. You have a proven track record of bringing successful projects to fruition; have proven leadership skills and excellent verbal and written communication ability.
Requirments:
BSEE and 5+ years full time Verilog/VHDL design experience, preferably in data communications
Complete FPGA designs using VHDL and/or Verilog HDL
Experience with Synplicity, Modelsim, large Xilinx and Altera devices
Proven track record of FPGA code from concept to production
SONET, POSPHY, Utopia, PCI bus, Gigabit Ethernet design experience is an asset
Contact: yilin@canada.com
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