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- 2004-01-15
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DESIGN ENGINEER
Requirements:
BSEE (MSEE preferred) or equivalent and five plus years ASIC design experience. Strong experience in Verilog HDL design and a strong working knowledge of block and top level design techniques, block and top level verification techniques, testbench design, chip synthesis, and physical layout; experience with Synopsys DC Compiler, PrimeTime, Formality, Tetramax, NC Verilog and the Unix environment; experience with ASIC synthesis techniques, DFT and ATPG techniques, floorplanning, timing analysis, timing closure techniques, and clock tree insertion in sub-micron designs are required. Experience with designs at 0.18 micron technology and knowledge of USB, Flash Card Formats, embedded processor designs, PC architectures and FPGA methodologies are a plus. Unix scripting and tools such as Perl. Proficiency in Windows-based PC software applications and excellent communication, written, and organizational skills are essential.
Great NY location near beaches with relocation provided
Design Engineer
BSEE/CE and a minimum of 7-10 years product design based on ASIC methods. RTL design with Verilog. Experience in Synopsys Design Compiler, VCS and Prime Time, scan insertion; back-end timing closure methods; various simulator tools and methods; UNIX environment including PERL; 0.35, 0.25 or 0.18 technologies; and PC platform architectures and compatibility issues are required. Multiple successful projects using this design flow must have been completed. Desired experience includes working knowledge of Viewlogic tool set and mixed schematic / RTL design; design validation through FPGA; physical level (transistor level) design experiences a plus; and knowledge of PC architectures and busses
used: PCI, PCI-Express, LPC will be beneficial. Proficiency in Windows-based PC software applications and excellent
Benefits: We offers a wide range of insurance benefits including health care (medical, dental and vision plans), life insurance and long term disability coverages. A 401(k) retirement savings plan offering various investment options is also available. All employees accrue a certain number of vacation days per year depending on length of service. Exempt employees are provided non-restricted sick leave subject to management's approval. Stock options are offered for all positions and some positions are bonus eligible. communication, written, and organizational skills are essential.
Great Long Island, NY area location, near the beaches - Relocation provided
Design Engineer
Requirements:
BSEE (MSEE Preferred) or equivalent plus 3-5 years CMOS ASIC design experience, Verilog HDL, Synposys, PrimeTime, and verification design flow experience. Must have used multiple design projects, taking these projects from initial specification/concept to final production release. Working knowledge of schematic capture design; knowledge of CMOS transistor level design of cells; knowledge of PC bus structure ? PCI/LPC/ISA and other modules are desirable. Knowledge of physical design is beneficial. Duties include Verilog design/verification of ASIC products and IP. This could be modifications to existing products, the design of new products ground up or the design of new products using internally designed IP or IP acquired from a third party. The responsibility is to take this design from spec through to silicon validation, making functional changes as required on bugs found in validation.
Benefits: We offers a wide range of insurance benefits including health care (medical, dental and vision plans), life insurance and long term disability coverages. A 401(k) retirement savings plan offering various investment options is also available. All employees accrue a certain number of vacation days per year depending on length of service. Exempt employees are provided non-restricted sick leave subject to management's approval. Stock options are offered for all positions and some positions are bonus eligible. communication, written, and organizational skills are essential.
Great NY area location, near the beaches - Relocation provided
Design Engineer
Requirements:
BSEE/MSEE or equivalent plus 5-10 years back-end design experience of complex SOC ASICS. Responsible for synthesis and back end timing closure of complex SOC ASIC devices. Includes top and core synthesis and script generation. Experience with DFT insertion and Pre and Post Static Timing Analysis using Primetime. Interface with layout team to achieve floorplanning. Able to perform clock tree insertion and timing closure. Astro or Encounter experience a plus. Able to
run Tetramax to create DFT production vectors. Able to perform power rail analysis. Proficiency in Windows-based PC
software applications and excellent communication, written, and organizational skills are essential.
Systems Architect
Requirements:
BSEE (MSEE preferred) or equivalent with 6+ years experience in embedded hardware systems design, ASIC development, SOC design, or design of networking communication products. This position requires in depth knowledge of communication standards including: TCP/IP, 802.3, 802.11, Bluetooth, GSM, CDMA, TDMA, USB, and IEEE-1394. Additionally, PCI, PC architecture, Embedded SOC architecture, and digital video experience are desirable. Responsibilities include participation in the development of new IC architectures by preparing "Product Architecture Specifications" and associated data sheets based on marketing/engineering requirements and the definition of effective architecture, logic and circuit design solutions. Duties include system definition, system architecture and implementation, architectural development of embedded systems, and creation of all associated design documentation. Product Architecture definition includes; detailed implementation and functional requirements, register definition, software interface definition, power management strategy, and system performance analysis. Knowledge of interrupt, DMA, SDRAM and Cache controllers as they relate to embedded systems a plus. Expertise in Verilog design, FPGA development, analog circuit simulation is also a plus. Proficiency in Windows-based PC software applications is a requirement. Must have excellent communication, written, organizational and analytical skills
Verification Engineer
Requirements:
BSEE/MSEE or equivalent and a minimum of 5-10 years ASIC design and verification experience. Strong background and experience required in Verilog and ASIC verification techniques plus testbench design. C++, System C, System Verilog, Vera experience are a plus. Job duties include design of Verilog test environments, transactors and BFMs; design directed and random tests for embedded ASIC devices; and investigate and implement new verification methodologies. Proficiency in Windows-based PC software applications and excellent communication, written, and organizational skills are essential.
Validation Engineer
Requirements:
BSEE or equivalent and three years of validation experience with in-depth knowledge of PC and 8051 microprocessor architecture, PCI and LPC bus, SMB, Windows OS, IO devices (IR, parallel port, serial port, floppy). Adept at C programming language, 8051 microprocessor firmware development. Desired experience includes hands on debugging experience of PC, IO hardware and software issues plus a good understanding of requirements for Silicon validation. VHDL and FPGA experience. Job responsibilities include system validation of ICs, customer application support (assisting FAEs) and resolving Test and QA chip-related issues. Proficiency in Windows-based PC software applications and excellent communication, written, and organizational skills are essential.
Systems Hardware Engineer
Requirements:
BSEE (MSEE a plus) or equivalent with a minimum of five years recent experience in FPGA/PLD design, system debug, and logic integration. This position requires strong skills in digital logic synthesis, and implementation preferably with Synplify_Pro and Xilinx ISE using HDL (Verilog or VHDL). Knowledge of current FPGA architecture, floorplanning, high-speed PCB design, PCB layout, and component level debug required. Also, familiarity with embedded microprocessor design, PCI bus protocol, Ethernet LAN, or Universal Serial Bus (USB), SOC design is desirable. Hands on experience and knowledge of lab equipment required. Self-starter with strong communication skills. Desired experience includes strong FPGA development knowledge, ASIC knowledge is a plus. Responsibilities include FPGA design, RTL design and systhesis, Logic design, system integration, board design, FPGA system debug.
Systems Validation Engineer
Requirements:
BSEE (MSEE preferred) plus a minimum of eight years experience in hardware debug and development of validation and diagnostic test software. Significant experience writing low-level, embedded, BIOS and/or Device Driver software in C is required. A strong hardware background and proficiency in using lab equipment (especially Oscilloscopes, Logic Analyzers, and Protocol Analyzers) to debug complex hardware/software interactions is essential. Desired experience includes knowledge of Ethernet, USB, Xilinx, PCI, embedded RISC CPU's (especially ARM), WinCE, Linux (in any
combination) is a plus. Responsibilities include writing low level test and diagnostic software for new connectivity (e.g., USB, Ethernet, etc.) silicon designs. This test software will be used as the basis to debug and validate the design in both FPGA and silicon environments.
Systems Hardware Engineer
Requirements:
BSEE (MSEE a plus) or equivalent with 5+ years combined experience in hardware design, validation, and debug. Primary responsibility will include validation and testing new silicon designs utilizing both industry conformance tools and custom validation test suites. A strong hardware background and proficiency in using lab equipment (especially Oscilloscopes, Logic Analyzers, and Protocol Analyzers) is essential. An understanding of ASIC processing and basic MOSFET principles is also required. Proficiency with software languages such as C or C++ is desired. Knowledge of Ethernet, USB, Xilinx FPGA, PCI, embedded RISC CPU's, HDL's (in any combination) is a plus. Self-starter with str
Best Regards,
Craig Townley
Phone: 919-388-7316
Toll free: 866-868-4971
E-mail: craig@townleygroup.com
Requirements:
BSEE (MSEE preferred) or equivalent and five plus years ASIC design experience. Strong experience in Verilog HDL design and a strong working knowledge of block and top level design techniques, block and top level verification techniques, testbench design, chip synthesis, and physical layout; experience with Synopsys DC Compiler, PrimeTime, Formality, Tetramax, NC Verilog and the Unix environment; experience with ASIC synthesis techniques, DFT and ATPG techniques, floorplanning, timing analysis, timing closure techniques, and clock tree insertion in sub-micron designs are required. Experience with designs at 0.18 micron technology and knowledge of USB, Flash Card Formats, embedded processor designs, PC architectures and FPGA methodologies are a plus. Unix scripting and tools such as Perl. Proficiency in Windows-based PC software applications and excellent communication, written, and organizational skills are essential.
Great NY location near beaches with relocation provided
Design Engineer
BSEE/CE and a minimum of 7-10 years product design based on ASIC methods. RTL design with Verilog. Experience in Synopsys Design Compiler, VCS and Prime Time, scan insertion; back-end timing closure methods; various simulator tools and methods; UNIX environment including PERL; 0.35, 0.25 or 0.18 technologies; and PC platform architectures and compatibility issues are required. Multiple successful projects using this design flow must have been completed. Desired experience includes working knowledge of Viewlogic tool set and mixed schematic / RTL design; design validation through FPGA; physical level (transistor level) design experiences a plus; and knowledge of PC architectures and busses
used: PCI, PCI-Express, LPC will be beneficial. Proficiency in Windows-based PC software applications and excellent
Benefits: We offers a wide range of insurance benefits including health care (medical, dental and vision plans), life insurance and long term disability coverages. A 401(k) retirement savings plan offering various investment options is also available. All employees accrue a certain number of vacation days per year depending on length of service. Exempt employees are provided non-restricted sick leave subject to management's approval. Stock options are offered for all positions and some positions are bonus eligible. communication, written, and organizational skills are essential.
Great Long Island, NY area location, near the beaches - Relocation provided
Design Engineer
Requirements:
BSEE (MSEE Preferred) or equivalent plus 3-5 years CMOS ASIC design experience, Verilog HDL, Synposys, PrimeTime, and verification design flow experience. Must have used multiple design projects, taking these projects from initial specification/concept to final production release. Working knowledge of schematic capture design; knowledge of CMOS transistor level design of cells; knowledge of PC bus structure ? PCI/LPC/ISA and other modules are desirable. Knowledge of physical design is beneficial. Duties include Verilog design/verification of ASIC products and IP. This could be modifications to existing products, the design of new products ground up or the design of new products using internally designed IP or IP acquired from a third party. The responsibility is to take this design from spec through to silicon validation, making functional changes as required on bugs found in validation.
Benefits: We offers a wide range of insurance benefits including health care (medical, dental and vision plans), life insurance and long term disability coverages. A 401(k) retirement savings plan offering various investment options is also available. All employees accrue a certain number of vacation days per year depending on length of service. Exempt employees are provided non-restricted sick leave subject to management's approval. Stock options are offered for all positions and some positions are bonus eligible. communication, written, and organizational skills are essential.
Great NY area location, near the beaches - Relocation provided
Design Engineer
Requirements:
BSEE/MSEE or equivalent plus 5-10 years back-end design experience of complex SOC ASICS. Responsible for synthesis and back end timing closure of complex SOC ASIC devices. Includes top and core synthesis and script generation. Experience with DFT insertion and Pre and Post Static Timing Analysis using Primetime. Interface with layout team to achieve floorplanning. Able to perform clock tree insertion and timing closure. Astro or Encounter experience a plus. Able to
run Tetramax to create DFT production vectors. Able to perform power rail analysis. Proficiency in Windows-based PC
software applications and excellent communication, written, and organizational skills are essential.
Systems Architect
Requirements:
BSEE (MSEE preferred) or equivalent with 6+ years experience in embedded hardware systems design, ASIC development, SOC design, or design of networking communication products. This position requires in depth knowledge of communication standards including: TCP/IP, 802.3, 802.11, Bluetooth, GSM, CDMA, TDMA, USB, and IEEE-1394. Additionally, PCI, PC architecture, Embedded SOC architecture, and digital video experience are desirable. Responsibilities include participation in the development of new IC architectures by preparing "Product Architecture Specifications" and associated data sheets based on marketing/engineering requirements and the definition of effective architecture, logic and circuit design solutions. Duties include system definition, system architecture and implementation, architectural development of embedded systems, and creation of all associated design documentation. Product Architecture definition includes; detailed implementation and functional requirements, register definition, software interface definition, power management strategy, and system performance analysis. Knowledge of interrupt, DMA, SDRAM and Cache controllers as they relate to embedded systems a plus. Expertise in Verilog design, FPGA development, analog circuit simulation is also a plus. Proficiency in Windows-based PC software applications is a requirement. Must have excellent communication, written, organizational and analytical skills
Verification Engineer
Requirements:
BSEE/MSEE or equivalent and a minimum of 5-10 years ASIC design and verification experience. Strong background and experience required in Verilog and ASIC verification techniques plus testbench design. C++, System C, System Verilog, Vera experience are a plus. Job duties include design of Verilog test environments, transactors and BFMs; design directed and random tests for embedded ASIC devices; and investigate and implement new verification methodologies. Proficiency in Windows-based PC software applications and excellent communication, written, and organizational skills are essential.
Validation Engineer
Requirements:
BSEE or equivalent and three years of validation experience with in-depth knowledge of PC and 8051 microprocessor architecture, PCI and LPC bus, SMB, Windows OS, IO devices (IR, parallel port, serial port, floppy). Adept at C programming language, 8051 microprocessor firmware development. Desired experience includes hands on debugging experience of PC, IO hardware and software issues plus a good understanding of requirements for Silicon validation. VHDL and FPGA experience. Job responsibilities include system validation of ICs, customer application support (assisting FAEs) and resolving Test and QA chip-related issues. Proficiency in Windows-based PC software applications and excellent communication, written, and organizational skills are essential.
Systems Hardware Engineer
Requirements:
BSEE (MSEE a plus) or equivalent with a minimum of five years recent experience in FPGA/PLD design, system debug, and logic integration. This position requires strong skills in digital logic synthesis, and implementation preferably with Synplify_Pro and Xilinx ISE using HDL (Verilog or VHDL). Knowledge of current FPGA architecture, floorplanning, high-speed PCB design, PCB layout, and component level debug required. Also, familiarity with embedded microprocessor design, PCI bus protocol, Ethernet LAN, or Universal Serial Bus (USB), SOC design is desirable. Hands on experience and knowledge of lab equipment required. Self-starter with strong communication skills. Desired experience includes strong FPGA development knowledge, ASIC knowledge is a plus. Responsibilities include FPGA design, RTL design and systhesis, Logic design, system integration, board design, FPGA system debug.
Systems Validation Engineer
Requirements:
BSEE (MSEE preferred) plus a minimum of eight years experience in hardware debug and development of validation and diagnostic test software. Significant experience writing low-level, embedded, BIOS and/or Device Driver software in C is required. A strong hardware background and proficiency in using lab equipment (especially Oscilloscopes, Logic Analyzers, and Protocol Analyzers) to debug complex hardware/software interactions is essential. Desired experience includes knowledge of Ethernet, USB, Xilinx, PCI, embedded RISC CPU's (especially ARM), WinCE, Linux (in any
combination) is a plus. Responsibilities include writing low level test and diagnostic software for new connectivity (e.g., USB, Ethernet, etc.) silicon designs. This test software will be used as the basis to debug and validate the design in both FPGA and silicon environments.
Systems Hardware Engineer
Requirements:
BSEE (MSEE a plus) or equivalent with 5+ years combined experience in hardware design, validation, and debug. Primary responsibility will include validation and testing new silicon designs utilizing both industry conformance tools and custom validation test suites. A strong hardware background and proficiency in using lab equipment (especially Oscilloscopes, Logic Analyzers, and Protocol Analyzers) is essential. An understanding of ASIC processing and basic MOSFET principles is also required. Proficiency with software languages such as C or C++ is desired. Knowledge of Ethernet, USB, Xilinx FPGA, PCI, embedded RISC CPU's, HDL's (in any combination) is a plus. Self-starter with str
Best Regards,
Craig Townley
Phone: 919-388-7316
Toll free: 866-868-4971
E-mail: craig@townleygroup.com
