Question: PLL bandwidth for a 2.5G CDR

[keen_observer]

Hi,

Does anyone know anything about the typical value of the PLL bandwidth for a 2.5Gb/s clock-data recovery integrated ciruict?

Thanks,

 

[eBridge]

Usually the bandwidth of the loop is often chosen to be
<1/10 of the oscillation frequency for sufficient phase margin
and stability, e.g. the bandwidth would be less than 500MHz if your VCO is 5GHz.

 

[keen_observer]

eBridge,
Thank you very much for the info. BTW, have you had idea about the peaking effect of the PLL closed-loop frequency response. What is the maximum peak before the loop resposne become unstable?

 

[eBridge]

Not sure about this question, I guess this would be a research topic. Did you search the literature to see what people have done ? One reference is http://www.commsdesign.com/main/2000/08/0008feat4.htm

 

[keen_observer]

最初由 eBridge 发布
Not sure about this question, I guess this would be a research topic. Did you search the literature to see what people have done ? One reference is http://www.commsdesign.com/main/2000/08/0008fea... [/B][/QUOTE] Thanks for the website.

 

[大屁股]

两位高手给解释一下，时钟锁相环的带宽是个什么概念？VCO是什么？是主振频率吗？

 

[阿搜]

VCO-Voltage control Oscillator

 

[keen_observer]

最初由 大屁股 发布
两位高手给解释一下，时钟锁相环的带宽是个什么概念？VCO是什么？是主振频率吗？

PLL bandwidth dictated the lock acquisition time & frequency deviation of the VCO output. Generally, smaller bandwidth will result a low jitter (or low frequency deviation) output from the VCO; however, small bandwidth also means slow acquisition time & degradation in the ability to track the transient in the reference source. Likewise; large bandwidth means fast acquisition time, and able to track fast transisent in reference source. But the price is the high jitter in VCO output.
Since PLL loop filter is a second order or third order system, stablility is also an issue when choosing the component values.

 

[大屁股]

明白了！
几位都是高手，以后有问题请教可不要推辞啊。