There're lots of papers on this, just post some here. I didn't get chance to read them, so not sure whether it is helpful. Are you working on PLL stuff ?
Yuriy M. Greshishchev, Peter Schvan, Jonathan L. Showell, Mu-Liang Xu, Jugnu J. Ojha, Jonathan E. Rogers A fully integrated sige receiver IC for 10-Gb/s data rate, IEEE Journal of Solid-State Circuits, vol. 35, pp. 1949 - 1957, December 2000.
Ching-Yuan Yang, Shen-Iuan Liu Fast-switching frequency synthesizer with a discriminator-aided phase detector, IEEE Journal of Solid-State Circuits, vol. 35, pp. 1445 - 1452, October 2000.
Woogeun Rhee, Bang-Sup Song, Akbar Ali A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order ΔΣ modulator, IEEE Journal of Solid-State Circuits, vol. 35, pp. 1453 - 1460, October 2000.
Yuriy M. Greshishchev, Peter Schvan SiGe clock and data recovery IC with linear-type PLL for 10-Gb/s SONET application, IEEE Journal of Solid-State Circuits, vol. 35, pp. 1353 - 1359, September 2000.
Yongsam Moon, Jongsang Choi, Kyeongho Lee, Deog-Kyoon Jeong, Min-Kyu Kim An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance, IEEE Journal of Solid-State Circuits, vol. 35, pp. 377 - 384, March 2000.
Hongil Yoon, Gi-Won Cha, Changsik Yoo, Nam-Jong Kim, Keum-Yong Kim, Chang Ho Lee, Kyu-Nam Lim, Kyuchan Lee, Jun-Young Jeon, Tae Sung Jung, Hongsik Jeong, Tae-Young Chung, Kinam Kim, Soo In Cho A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM, IEEE Journal of Solid-State Circuits, vol. 34, pp. 1589 - 1599, November 1999.
Henrik O. Johansson A simple precharged CMOS phase frequency detector, IEEE Journal of Solid-State Circuits, vol. 33, pp. 295 - 299, February 1998.
C. R. Ryan Applications of a four-quadrant multiplier, IEEE Journal of Solid-State Circuits, vol. 5, pp. 45 - 48, February 1970.