请问是否有用过TI的6205的高手？

[deers]

这芯片有2个复位脚PCI_RST和DEVICE_RST，请问有什么特别不同用处吗？具体应用是该怎么接？
多谢！

 

[keen_observer]

最初由 deers 发布
这芯片有2个复位脚PCI_RST和DEVICE_RST，请问有什么特别不同用处吗？具体应用是该怎么接？
多谢！

Not sure about the PCI RESET, I think it allows this chip to be reset by another chip through the PCI.

for the device RESET can be hard-wired to a source that is capable of driving 0V and 5/3.3V. In this case, it can be tied to an I/O port of an onboard micro-controller such as 68HC11, or it can be tied any analog output that can output 0V or 5/3.3V. In this case, the RESET is an active LOW (0V)input. A logic LOW is required to active the reset function. There is timing requirement associated with the use of the RESET signal.

 

[WarmHearted]

Connect the PCI_RST to PCI reset pin if you use PCI for this chip. Should pull up/down if you do not use PCI(you should check if it has internal pull up/down)

Connect the DEVICE_RST to Globle reset pin in your system.

Or you can connect both to your system globle reset, also works fine.

All in one, base on application and check the datasheet and appnote.

 

[deers]

Thanks keen_observer and WarmHearted.
Because I had some problems on PCI bus, I'd thought that might be an reset issue.
And as we don't have other processors on board, for now we direct connect those 2 reset together as a solution.
But I still have a PCI bus problem:
There is a parity-error bit in the state register of the PCI config registers. I found that it was very easy to be "1". Does that mean that the DSP finds the parity error on the PCI bus? And usually it happens when I do not plug the card properly?
I appreciate your helps.

 

[keen_observer]

最初由 deers 发布
Thanks keen_observer and WarmHearted.
Because I had some problems on PCI bus, I'd thought that might be an reset issue.
And as we don't have other processors on board, for now we direct connect thos...

Generally, the PCI RESET can be left floating without negative effect. The power up RESET is more important. A lot of chips required a hardware RESET when the card first power up for realiable operation. A special "voltage suprevisor" chip is designed for this task.

The parity problem simply implies there are bit errors detected at the BUS interface being monitored. This would be resulted from the improper power up RESET. First thing to check is to make sure there is a hardware RESET after power up.