最初由 spacespace 发布
0.13u with 38M gates, that is too much. I am not saying that is impossible, I am just saying it is too hard. How big the chip going to be, I am not sure if there is any package can fit into it. And how much power it going to consume, must like a heater. 0.09u, there is too many unknow factors, when desing move toward deep sub-micron, a lot of things people do not know. Everyone is learning when they move forward.
Yeah, most Cisco designs are under 0.13u, but does not mean that is cheaper to them. The reason they have to go with 0.13u is that they require high speed IO, DDR RAM and other high speed macro support which is only available in 0.13 technology. The price to Cisco is definite not cheaper. Actually IBM or TI take the price advantage of the technology, they can make more money, not Cisco. But all those based on one assumption, high volume. The fact is that in the high-end ASIC cummunication area, the volume is really low, low volume means low profit, or even losing money.
At the begining of the project, everyone will claim high volume to bargain for the price. But after the project is done, you will find they only want 1000 parts per year. How many wafers for 1000 parts? probably just 3 wafers. That is why not many company would like to support high-end customers, like Cisco. Do u work for Cisco?
